As shown in FIG. 1, two (or multiple) dies can be stacked in what are commonly referred to as three-dimensional integrated circuit packages to provide dense interconnection (e.g., 3000 or more interconnects) between a first die (e.g., processor) 105 and a second die (e.g., memory) 107, which provides increased bandwidth between the dies. In order to provide signal and power supply lines to the dies (especially to the first, upper die), however, through silicon vias (TSVs) 109 coming up through the second (lower) die may be employed.
In some embodiments, the first (top) die is a processor, while the second (lower) die comprises a dense memory device. Bumps on the lower die connect to a package substrate, which couples the package to external connections such as to a motherboard. FIG. 2A is an exemplary high-level layout diagram for a memory die 107. The memory is organized into individual banks (Mem. Bank 205). The memory die also includes peripheral I/O circuit blocks and logic, clock, and timing circuit blocks in the middle. The through silicon vias are processed from the back side of the memory die and land on pre-assigned contact pads, e.g., at the interface with the upper (processor) die.
FIG. 2B shows one possible way of positioning the contact pads for TSVs landing across the entire memory die. Unfortunately, as seen from the figure, the TSVs come through memory bank sections and end up at various asymmetric or irregular places. Accordingly, improved solutions are desired.